Efficient Implementation of SPEEDY Block Cipher on Cortex-M3 and RISC-V Microcontrollers

The SPEEDY block cipher family announced at the CHES 2021 shows excellent performance on hardware architectures. Due to nature of hardware-friendly design SPEEDY, algorithm has low for software implementations. In particular, 6-bit S-box and bit permutation operations are inefficient in implementations, where it performs word-wise computations. We implemented a 32-bit microcontroller first time by applying bit-slicing techniques. optimized encryption results ARM Cortex-M3 SPEEDY-5-192, SPEEDY-6-192, SPEEDY-7-192 65.7, 75.25, 85.16 clock cycles per byte (i.e., cpb), respectively. It showed better than AES-128 constant-time implementation GIFT same platform. RISC-V, 81.9, 95.5, 109.2 byte, which outperformed previous works. Finally, we conclude that can show efficient low-end embedded environments.